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During the iterative optimization timing process from the post-routing to the sign-off stage, a significant time-cost issue was incurred due to the repetitive execution of static timing analysis. Therefore, a standard cell feature extraction algorithm was devised and the standard cell delay prediction problem was modeled. Utilizing the recurrent neural network(RNN) as the foundation, the cell-delay prediction model(C-DPM) was constructed to delve into the nonlinear mapping relationship between standard cell characteristics and delay, facilitating rapid prediction of standard cell delay. To assess the delay prediction performance of C-DPM for different design modules under various process, voltage, and temperature conditions, experiments were conducted on six different design modules with sub-30 nm process. The experimental results revealed that the maximum average absolute error in delay prediction for C-DPM ranged from 0.519 ps to 1.310 ps, while the minimum average absolute error in delay prediction ranged from 0.380 ps to 1.016 ps. This demonstrated that C-DPM could trade off minimal error for a reduction in time overhead, thereby accelerating the efficiency of physical design.
[1] GARGINI P.The international technology roadmap for semiconductors[EB/OL].(2022-01-02)[2023-05-16].http://www.itrs2.net/itrs-reports.html.
[2] ABIODUN O I,JANTAN A,OMOLARA A E,et al.State-of-the-art in artificial neural network applications:a survey[J].Heliyon,2018,4(11):1-41.
[3] 贺旭，王耀，傅智勇，等.敏捷设计中基于机器学习的静态时序分析方法综述[J].计算机辅助设计与图形学学报，2023,35(4):640-652.HE X,WANG Y,FU Z Y,et al.A survey on machine learning-based technology for static timing analysis in agile design[J].Journal of computer-aided design & computer graphics,2023,35(4):640-652.
[4] LEE Y,WATERMAN A,COOK H,et al.An agile approach to building RISC-V microprocessors[J].IEEE micro,2016,36(2):8-20.
[5] BARBOZA E C,SHUKLA N,CHEN Y,et al.Machine learning-based pre-routing timing prediction with reduced pessimism[C]//Proceedings of the 56th Annual Design Automation Conference.New York:ACM Press,2019:1-6.
[6] KAHNG A B,LIN B,NATH S.Enhanced metamodeling techniques for high-dimensional IC design estimation problems[C]//Design,Automation & Test in Europe Conference & Exhibition.Piscataway:IEEE Press,2013:1861-1866.
[7] KAHNG A B,LIN B,NATH S.High-dimensional metamodeling for prediction of clock tree synthesis outcomes[C]//ACM/IEEE International Workshop on System Level Interconnect Prediction.New York:ACM Press,2013:1-7.
[8] KWON Y,JUNG J,HAN I,et al.Transient clock power estimation of pre-CTS netlist[C]//IEEE International Symposium on Circuits and Systems.Piscataway:IEEE Press,2018:1-4.
[9] CHENG H H,JIANG I H R,OU O.Fast and accurate wire timing estimation on tree and non-tree net structures[C]//57th ACM/IEEE Design Automation Conference.New York:ACM Press,2020:1-6.
[10] HAN S S,KAHNG A B,NATH S,et al.A deep learning methodology to proliferate golden signoff timing[C]//Design,Automation & Test in Europe Conference & Exhibition.Piscataway:IEEE Press,2014:1-6.
[11] KAHNG A B,LUO M L,NATH S.SI for free:machine learning of interconnect coupling delay and transition effects[C]//ACM/IEEE International Workshop on System Level Interconnect Prediction.New York:ACM Press,2015:1-8.
[12] LAI S W,XU L H,LIU K,et al.Recurrent convolutional neural networks for text classification[C]//Proceedings of the 29th AAAI Conference on Artificial Intelligence.New York:ACM Press,2015:2267-2273.
Basic Information:
DOI：10.13705/j.issn.1671-6841.2023213
China Classification Code:TN40;TP183
Citation Information:
[1]YOU Huiqing,HUANG Pengcheng,ZHAO Zhenyu ,et al.A Standard Cell Delay Prediction Method Based on RNN[J].Journal of Zhengzhou University(Natural Science Edition),2025,57(03):28-34.DOI:10.13705/j.issn.1671-6841.2023213.
Fund Information:
国家自然科学基金项目(62034005); 湖南省科技创新计划资助项目(2023RC3014); 湖南省自然科学基金项目(2023JJ30637,2022JJ10066); 青年科技人才支持计划(ZD0102088845)
2023-09-07
2023
2024-04-23
2025-06-17
2025
2
2024-04-30
2024-04-30
2024-04-30